RAMSBDIS=0, LPTMR3SEL=00, LPTMR2SEL=00, RAMBPEN=0, LPTMR1SEL=00, LPTMR0SEL=00
SOPT1 Configuration Register
LPTMR0SEL | LP Timer Channel0 Select 0 (00): CMP[0] output 1 (01): CMP[1] output 2 (10): CMP[2] output |
LPTMR1SEL | LP Timer Channel1 Select 0 (00): Pad PTE4 1 (01): Pad PTF4 2 (10): Pad PTG1 |
LPTMR2SEL | LP Timer Channel2 Select 0 (00): Pad PTD6 1 (01): Pad PTF3 2 (10): Pad PTG5 |
LPTMR3SEL | LP Timer Channel3 Select 0 (00): Pad PTD5 1 (01): Pad PTG0 2 (10): Pad PTG6 |
RAMSBDIS | Disable source bias of System SRAM arrays during VLPR and VLPW modes. 0 (0): Source bias of System SRAM enabled during VLPR and VLPW modes. 1 (1): Source bias of System SRAM disabled during VLPR and VLPW modes. |
RAMBPEN | RAM Bitline Precharge Enable 0 (0): Bitline precharge of system SRAM disabled during VLPR and VLPW modes. 1 (1): Bitline precharge of system SRAM enabled during VLPR and VLPW modes. |