Freescale Semiconductor /MKM34Z7 /SIM /SOPT1_CFG

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Interpret as SOPT1_CFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)LPTMR0SEL 0 (00)LPTMR1SEL 0 (00)LPTMR2SEL 0 (00)LPTMR3SEL 0 (0)RAMSBDIS 0 (0)RAMBPEN

RAMSBDIS=0, LPTMR3SEL=00, LPTMR2SEL=00, RAMBPEN=0, LPTMR1SEL=00, LPTMR0SEL=00

Description

SOPT1 Configuration Register

Fields

LPTMR0SEL

LP Timer Channel0 Select

0 (00): CMP[0] output

1 (01): CMP[1] output

2 (10): CMP[2] output

LPTMR1SEL

LP Timer Channel1 Select

0 (00): Pad PTE4

1 (01): Pad PTF4

2 (10): Pad PTG1

LPTMR2SEL

LP Timer Channel2 Select

0 (00): Pad PTD6

1 (01): Pad PTF3

2 (10): Pad PTG5

LPTMR3SEL

LP Timer Channel3 Select

0 (00): Pad PTD5

1 (01): Pad PTG0

2 (10): Pad PTG6

RAMSBDIS

Disable source bias of System SRAM arrays during VLPR and VLPW modes.

0 (0): Source bias of System SRAM enabled during VLPR and VLPW modes.

1 (1): Source bias of System SRAM disabled during VLPR and VLPW modes.

RAMBPEN

RAM Bitline Precharge Enable

0 (0): Bitline precharge of system SRAM disabled during VLPR and VLPW modes.

1 (1): Bitline precharge of system SRAM enabled during VLPR and VLPW modes.

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